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HM-65642
8K x 8 Asynchronous CMOS Static RAM
Description
The HM-65642 is a CMOS 8192 x 8-bit Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and RAMs. The HM-65642 is ideally suited for use in microprocessor based systems. In particular, interfacing with the Intersil 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G) input. The HM-65642 is a full CMOS RAM which utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range.
May 2002
Features
* Full CMOS Design * Six Transistor Memory Cell * Low Standby Supply Current . . . . . . . . . . . . . . . . 100A * Low Operating Supply Current. . . . . . . . . . . . . . . 20mA * Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns * Low Data Retention Supply Voltage . . . . . . . . . . . 2.0V * CMOS/TTL Compatible Inputs/Outputs * JEDEC Approved Pinout * Equal Cycle and Access Times * No Clocks or Strobes Required * Gated Inputs * No Pull-Up or Pull-Down Resistors Required * Easy Microprocessor Interfacing * Dual Chip Enable Control
Ordering Information
PACKAGE CERDIP JAN# TEMPERATURE RANGE -40oC to +85oC -55oC to +125oC 29205BXA (NOTE 1) 150ns/75A (NOTE 1) 150ns/150A HM1-65642-9 (NOTE 1) 200ns/250A PKG. NO. F28.6 F28.6
NOTE: 1. Access Time/Data Retention Supply Current.
Pinout
HM-65642 (CERDIP) TOP VIEW
NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 DQ0 11 DQ1 12 DQ2 13 GND 14 28 VCC 27 W 26 E2 25 A8 24 A9 23 A11 22 G 21 A10 20 E1 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3
PIN A DQ E1 E2 W G NC GND VCC
DESCRIPTION Address Input Data Input/Output Chip Enable Chip Enable Write Enable Output Enable No Connections Ground Power
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
FN3005.2
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HM-65642 Functional Diagram
A9 ROW ADDRESS BUFFERS A8 A12 A7 A6 A5 A4 A3 A ROW DECODER 8 256
256 x 256 MEMORY ARRAY
A 8
256 COLUMN ADDRESS BUFFERS A2 A1 A0 A10 A11
A 5 A 5 COLUMN SELECT (8 OF 256)
8 W
G
E1
8 E2 1 OF 8 DQ
TRUTH TABLE MODE Standby (CMOS) Standby (TTL) E1 X VIH X Enable (High Z) Write Read VIL VIL VIL E2 GND X VIL VIH VIH VIH W X X X VIH VIL VIH G X X X VIH X VIL
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HM-65642
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for All Grades . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
JC Thermal Resistance (Typical) JA CERDIP Package . . . . . . . . . . . . . . . . 45oC/W 8oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-65642-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . +2.2V to VCC +0.3V
DC Electrical Specifications
SYMBOL ICCSB1 ICCSB2 ICCDR ICCEN ICCOP II IIOZ VCCDR VOH1 VOH2 VOL
VCC = 5V 10%; TA = -40oC to +85oC (HM-65642-9) LIMITS
PARAMETER Standby Supply Current (CMOS) Standby Supply Current (TTL) Data Retention Supply Current Enabled Supply Current Operating Supply Current (Note 1) Input Leakage Current Input/Output Leakage Current Data Retention Supply Voltage Output High Voltage Output High Voltage (Note 2) Output Low Voltage TA = +25oC PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2)
MIN -1.0 -1.0 2.0 2.4 VCC -0.4 -
MAX 250 5 150 5 20 +1.0 +1.0 0.4
UNITS A mA A mA mA A A V V V V
TEST CONDITIONS E2 = GND, VCC = 5.5V E2 = 0.8V or E1 = 2.2V, VCC = 5.5V E2 = GND, VCC = 2.0V E2 = 2.2V, E1 = 0.8V, VCC = 5.5V, IIO = 0mA f = 1MHz, E1 = 0.8V, E2 = 2.2V, VCC = 5.5V, IIO = 0mA VI = VCC or GND, VCC = 5.5V E2 = GND, VIO = VCC or GND, VCC = 5.5V
IOH = -1.0mA, VCC = 4.5V IOH = -100A, VCC = 4.5V IOL = 4.0mA, VCC = 4.5V
Capacitance
SYMBOL CI CIO NOTES:
MAX 12 14
UNITS pF pF
TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
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HM-65642
AC Electrical Specifications
SYMBOL READ CYCLE (1) TAVAX (2) TAVQV (3) TE1LQV (4) TE2HQV (5) TGLQV (6) TE1LQX (7) TE2HQX (8) TGLQX (9) TE1HQZ (10) TE2LQZ (11) TGHQZ (12) TAXQX WRITE CYCLE (13) TAVAX (14) TWLWH (15) TE1LE1H (16) TE2HE2L (17) TAVWL (18) TAVE1L (19) TAVE2H (20) TWHAX (21) TE1HAX (22) TE2LAX (23) TDVWH (24) TDVE1H (25) TDVE2L (26) TWHDX (27) TE1HDX (28) TE2LDX (29) TWLQZ (30) TWHQX NOTES: 1. Input pulse levels: 0V to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. Write Cycle Time Write Pulse Width Chip Enable to End of Write Chip Enable to End of Write Address Setup Time Address Setup Time Address Setup Time Write Recovery Time Write Recovery Time Write Recovery Time Data Setup Time Data Setup Time Data Setup Time Data Hold Time Data Hold Time Data Hold Time Write Enable Low to Output Off Write Enable High to Output On Late Write Early Write Early Write Late Write Early Write Early Write Late Write Early Write Early Write Late Write Early Write Early Write E1 E2 E1 E2 E1 E2 E1 E2 E1 E2 150 90 90 90 0 0 0 10 10 10 60 60 60 5 10 10 5 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 2, 3) (Notes 2, 3) Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable Access Time Output Enable Access Time Chip Enable Valid to Output On Chip Enable Valid to Output On Output Enable Valid to Output On Chip Enable Not Valid to Output Off Chip Enable Not Valid to Output Off Output Enable Not Valid to Output Off Output Hold From Address Change E1 E2 E1 E2 E1 E2 150 10 10 5 10 150 150 150 70 50 60 50 ns ns ns ns ns ns ns ns ns ns ns ns (Notes 1, 3) (Notes 1, 3) (Notes 2, 3) (Notes 1, 3) (Notes 1, 3) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) (Notes 2, 3) VCC = 5V 10%; TA = -40oC to +85oC (HM-65642-9) LIMITS PARAMETER MIN MAX UNITS TEST CONDITIONS
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HM-65642 Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in mind. Data Retention voltage and supply current are guaranteed over the operating temperature range. The following rules ensure data retention:
1. The RAM must be kept disabled during data retention. This is accomplished by holding the E2 pin between -0.3V and GND. 2. During power-up and power-down transitions, E2 must be held between -0.3V and 10% of VCC. 3. The RAM can begin operating one TAVAX after VCC reaches the minimum operating voltage of 4.5V.
DATA RETENTION MODE VCC 4.5V VIH E2 VCCOR TAVAX
GND
FIGURE 1. DATA RETENTION
Read Cycles
TAVAX (1) A ADDRESS 1 TAVQV (2) Q ADDRESS 2 TAXQX (12) DATA 1 DATA 2
FIGURE 2. READ CYCLE I: W, E2 HIGH; G, E1 LOW
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HM-65642 Read Cycles
TAVAX (1) A TAVQV (2) E1 TE1LQV (3) TE1LQX (6) E2 TE2HQV (4) TE2HQX (7) G TGLQV (5) TGLQX (8) Q TGHQZ (11) TE2LQZ (10) TE1HQZ (9)
FIGURE 3. READ CYCLE II: W HIGH
Write Cycles
TAVAX (13) A TAVWL (17) W TWLWH (14) TWHAX (20)
E1
E2 TWHQX (30) TDVWH (23) D TWLQZ (29) Q TWHDX (26)
FIGURE 4. WRITE CYCLE I: LATE WRITE
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HM-65642 Write Cycles
TAVAX (13) A TE1LE1H (15)
TAVE1L (18) W E1
TE1HAX (21)
E2 TDVE1H (24) D TE1HDX (27)
FIGURE 5. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1
TAVAX (13) A TE2HE2L (16) W E1 TAVE2H (19) TE2LAX (22)
E2 TDVE2L (25) D TE2LDX (28)
FIGURE 6. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2
Typical Performance Curve
-3 -4 -5 LOG (ICC/(1A)) -6 -7 -8 -9 -10 -11 -12 -55 -35 -15 5 25 45 65 85 105 125 VCC = 2.0V
TA (oC)
FIGURE 7. TYPICAL ICCDR vs TA
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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